This invention relates to treating semiconductor devices with deuterium to improve operating characteristics, and in particular to improve hot-carrier reliability of transistors, and to semiconductor devices resulting from such treatment.
Degradation of operating performance of semiconductor devices (for example CIMOS transistor device structures) due to hot carrier effects attributed to hydrogen desorption at an oxide (typically silicon oxide)/semiconductor(typically silicon) interface has been recognized and studied for many years. One proposed solution has been to subject such devices to hydrogen (H2) annealing but in practice this has been recognized as ineffective. A more effective approach to alleviating the problem has been to include a deuterium annealing step at a convenient point in the device fabrication process manufacturing process, before or subsequent to contact formation and interconnects (metallization). Known deuterium annealing processes include, for example, those disclosed by U.S. Pat. No. 5, 872,387, in J. W. Lyding, K. Hess and I.C. Kizilyalli, xe2x80x9cReduction of Hot Electron Degradation in Metal Oxide Semicondutor Transistors by Deuterium Processing,xe2x80x9d Appl. Phys. Lett. 68, p. 2526 (1996), and in I. C. Kizilyalli, J. W. Lyding, and K. Hess, xe2x80x9cDeuterium post-metal annealing of MOSFETs for improved hot carrier reliability,xe2x80x9d IEEE Electron Device Lett., vol 18, p. 81, March 1997, all of which, together with the publications to which subsequent reference is made herein, are hereby incorporated herein by reference as if each had been individually incorporated by reference and fully set forth herein.
While the beneficial impact of deuterium annealing on semiconductor device operating lifetime has been quite dramatic, and has improved, state of the art semiconductor devices remain prone to hot carrier problems and further improvements in processing to further alleviate this problem are desirable.
In one aspect, the present invention provides a process for manufacturing a semiconductor device including a semiconductor region and an insulating layer having an interface with the semiconductor region, comprising the steps of exposing the semiconductor device to an ambient including deuterium wherein said deuterium has a partial pressure in excess of atmospheric pressure to form a concentration of deuterium at the interface between said semiconductor region and said insulating layer. The deuterium annealing process may be carried out at any convenient point during the fabrication process but it is preferred to implement it after completion of all high temperature processing steps, i.e. typically after contact formation, to reduce deuterium dissipation which otherwise may occur. The invention has been found to result it, significant advantages in increasing lifetime of semiconductor devices subject to hot carrier stress during operation, as compared to hydrogen annealing and deuterium annealing at atmospheric pressure.
In another aspect, the present invention provides a process for manufacturing a semiconductor device including at least one insulating layer overlying a semiconductor region, comprising the steps of exposing said semiconductor device to an ambient including deuterium wherein said deuterium has a partial pressure in excess of atmospheric pressure. This aspect of the invention may be utilized to provide a high concentration of deuterium in interlevel dielectric layers used to insulate adjacent metal circuitry layers in semiconductor devices.
While a 100% deuterium ambient is preferred for the annealing process, other ambients may be used, for example a nitrogen/deuterium ambient, provided the deuterium partial pressure is above one atmospheric pressure. Thus, for example, a 50% deuterium 50% nitrogen ambient at 10 atmospheres may be used, resulting in a deuterium partial pressure of 5 atmospheres.
It is contemplated that deuterium pressures up to about 100 atmospheres may be technologically significant but for commercial purposes, pressures above about 15 atmospheres are less likely to be of interest. At deuterium pressures above about 10 atmospheres, additional interface defects may arise under some temperature conditions so that, for commercially practical purposes, deuterium pressures not exceeding about 10 atmospheres are regarded as preferable in practicing the invention. For any particular set of process parameters, the deuterium concentration resulting from the annealing process will increase with increasing deuterium pressure.
A process according to the invention may be carried out at temperatures of about 150xc2x0 C. and above, typically up to about 600xc2x0 C. and advantageously over the approximate range 350xc2x0 C.-450xc2x0 C. One advantage of the invention is that deuterium annealing carried out at deuterium pressures in excess of one atmosphere permit a reduction in processing temperature while resulting in equivalent benefits associated with deuterium annealing carried out at one atmosphere. For example, deuterium annealing at about 350xc2x0 C. carried out in accordance with the invention has been found to produce similar benefits as deuterium processing at one atmosphere carried out in a temperature range of about 400xc2x0 C. to 450xc2x0 C.
A deuterium annealing process embodying the invention may typically be carried out over a period in excess of about 5 minutes, typically from about 10 minutes, preferably 30 minutes, to about 3 hours. The particular combination of deuterium superatmospheric pressure, annealing temperature and annealing time may be empirically determined and be affected, for example, by the particular device structure and the deuterium concentration desired at the target location. Increasing deuterium pressure permits a shorter annealing time to achieve a particular deuterium concentration at the target location. The deuterium concentration at the target location should be at least 1016 atoms/cc, desirably is in excess of about 1018 atoms/cc, and advantageously may be in the range 1019 to 1021 atoms/cc.
One problem related to carrying out post metal deuterium annealing is that current MOS technologies often employ silicon nitride sidewall spacers adjacent the gate insulator, and sometimes a barrier layer, such as a silicon nitride cap, is formed over the gate and other contacts, through which the deuterium has to penetrate. It has been found that an annealing process embodying the invention, using deuterium at superatmospheric pressure, is effective in improving deuterium penetration of such sidewall spacers and barrier layers. Consequently, the employment of a deuterium annealing process in accordance with the invention becomes more feasible as a final thermal process in semiconductor device fabrication which is advantageous in minimizing deuterium dissipation. Reference to a thermal process is intended to include any processing involving one or more cycles involving heating followed by cooling, e.g. deposition processing, which typically may occur at temperatures around 300xc2x0 C. and upwards, in part dependent on the processing time involved.
The invention has particular application in processing CMOS structures in order to introduce a concentration of deuterium at the gate oxide/silicon interface, and advantageously is carried out after contact formation as the final thermal processing step. Suitably, the deuterium annealing process is carried out in a 100% deuterium ambient at a superatmospheric pressure up to about 6 atmospheres. Annealing temperatures in the approximate range 350xc2x0 C. to 600xc2x0 C. may conveniently be used but temperatures toward the lower end of this range, suitably 350xc2x0 C., are preferred and annealing periods may typically range from about 30 minutes to about 3 hours. Deuterium processing of CMOS transistors in accordance with the invention has been found to be advantageous in facilitating incorporation of higher concentrations of deuterium at the gate silicon oxide/silicon interface, resulting in greater lifetime improvement in comparison to ambient (atmospheric pressure) deuterium annealing. It has been discovered that high pressure deuterium carried out in accordance with the invention also advantageously not only can increase the magnitude of the improvement but also can shorten the annealing time required to produce a given concentration of deuterium at the gate oxide/silicon interface.
As reported in J. Lee, K. Cheng, Z. Chen, K. Hess, J. W. Lyding, Y-K Kim, H-S Lee, Y-W kim and K-P suh, Application of High Pressure Deuterium Annealing for Improving the Hot carrier reliability of CMOS Transistors,xe2x80x9d IEEE Elec. Dev. Lett., 21, p. 221 (2000), the efficacy of annealing in a superatmospheric deuterium ambient has been demonstrated in fabrication of complementary metal-oxide-semiconductor (CMOS) transistors where it has been found that a greater than tenfold increase in device reliability lifetime can be achieved compared to deuterium processing at ambient pressure as reported in J. W. Lyding, Karl Hess, and I. C. Kizilyalli, xe2x80x9cReduction of Hot Electron Degradation in Metal Oxide Semiconductor Transistors by Deuterium Processing,xe2x80x9d Appl. Phys. Lett. 68, 2526 (1996). Furthermore, it is possible to significantly lower processing temperatures and still achieve a large lifetime improvement by processing at high deuterium pressure. This is particularly significant in view of the low thermal budgets of the latest CMOS technologies. High pressure deuterium processing in accordance with the invention appears likely to be beneficial for MOS technologies such as n-channel (NMOS) and p-channel (PMOS) devices, flash memory devices, the drive transistor and storage capacitor in dynamic random access memory (DRAM), static random access memory (SRAM) transistor, bipolar technologies, charge-coupled display (CCD) devices, biCMOS technology, silicon-germanium MOS devices, and compound semiconductor devices comprised of elements from columns III and V of the periodic table. High pressure deuterium embodying the invention may be used to incorporate high concentrations of deuterium in the interlayer dielectrics used to insulate adjacent metal circuitry layers in integrated circuits, e.g. microchips employing MOS, particularly CMOS, technology processing, as there is evidence that deuterium is beneficial in those locations. Solar cells based on crystalline silicon, polycrystalline silicon, and amorphous hydrogenated silicon are also known to benefit from deuterium incorporation and would therefore be improved by high pressure deuterium processing in accordance with the invention.